1. Field of the Invention
Generally, the present invention relates to the formation of integrated circuits, and, more particularly, to the formation of metallization layers including highly conductive metals, such as copper, embedded into a dielectric material.
2. Description of the Related Art
In an integrated circuit, a very large number of circuit elements, such as transistors, capacitors, resistors and the like, are formed in or on an appropriate substrate, usually in a substantially planar configuration. Due to the large number of circuit elements and the required complex layout of advanced integrated circuits, the electrical connections of the individual circuit elements are generally not established within the same level on which the circuit elements are manufactured. Typically, such electrical connections are formed in one or more additional “wiring” layers, also referred to as metallization layers. These metallization layers generally include metal-containing lines, providing the inner-level electrical connection, and also include a plurality of inter-level connections, also referred to as vias, filled with an appropriate metal. The vias provide electrical connection between two neighboring stacked metallization layers, wherein the metal-containing lines and vias may also be commonly referred to as interconnect structures.
Due to the continuous shrinkage of the feature sizes of circuit elements in modern integrated circuits, the number of circuit elements for a given chip area, that is the packing density, also increases, thereby requiring an even larger increase in the number of electrical interconnections to provide the desired circuit functionality. Therefore, the number of stacked metallization layers may increase and the dimensions of the individual lines and vias may be reduced as the number of circuit elements per chip area becomes larger. The fabrication of a plurality of metallization layers entails extremely challenging issues to be solved, such as mechanical, thermal and electrical reliability of a plurality of stacked metallization layers. As the complexity of integrated circuits advances and brings about the necessity for conductive lines that can withstand moderately high current densities, semiconductor manufacturers are increasingly replacing the well-known metallization metal aluminum with a metal that allows higher current densities and hence allows a reduction in the dimensions of the interconnections and thus the number of stacked metallization layers. For example, copper and alloys thereof are materials that are used to increasingly replace aluminum due to their superior characteristics in view of higher resistance against electromigration and significantly lower electrical resistivity when compared with aluminum. Despite these advantages, copper and copper alloys also exhibit a number of disadvantages regarding the processing and handling in a semiconductor facility. For instance, copper may not be efficiently applied onto a substrate in larger amounts by well-established deposition methods, such as chemical vapor deposition (CVD), and also may not be effectively patterned by the usually employed anisotropic etch procedures. Consequently, in manufacturing metallization layers including copper, the so-called damascene technique (single and dual) is therefore preferably used wherein a dielectric layer is first applied and then patterned to receive trenches and/or vias, which are subsequently filled with copper or copper alloys.
It turns out that the process of etching vias and trenches in the dielectric layer according to the damascene regime may significantly affect the overall production yield during the formation of advanced semiconductor devices having copper-based metallization layers owing to substrate damage caused by plasma-assisted etch processes. With reference to FIGS. 1a-1c, a typical conventional process flow will now be described in more detail so as to more clearly demonstrate the problems involved in forming highly scaled metal lines in a dielectric material according to a dual damascene process, in which vias are formed prior to corresponding trenches connected to the vias, wherein this approach is often called “via first trench last” approach.
FIG. 1a schematically shows a cross-sectional view of a semiconductor device 100 comprising a substrate 101, which may be provided in the form of a bulk silicon substrate, a silicon-on-insulator (SOI) substrate and the like, wherein the substrate 101 may also represent a device layer having formed therein individual circuit elements, such as transistors, capacitors, lines, contact portions and the like. For convenience, any such circuit elements are not shown in FIG. 1a. The device 100 comprises a first die region 120A and a second die region 120B, wherein the first die region 120A may represent an “inner” region that receives metal lines and vias, whereas the second die region 120B may represent a die seal region, a measurement region and the like, which is to receive a metal formed of continuously stacked metal regions so as to delineate, when the second die region represents a delineation trench, the first die region 120A from the second die region 120B. The device 100 further comprises a dielectric layer 102 formed above the substrate 101, wherein the layer 102 may represent a dielectric material enclosing the individual circuit elements, also referred to as contact layer, or the layer 102 may represent a portion of a lower lying metallization layer, in which any metal-filled vias (not shown) may be embedded. Depending on the specific design of the device 100, or the function of the layer 102, it may be comprised of a conventional dielectric material such as silicon dioxide, silicon nitride, or may comprise a low-k dielectric material such as, for instance, hydrogen enriched silicon oxycarbide (SiCOH). A metal line 103A is formed within the first die region 120A and above the substrate 101 and at least partially within the layer 102. The metal line 103A may be comprised of a copper-containing metal including conductive barrier layers (not shown) so as to enhance adhesion of the metal line to the surrounding material and reduce diffusion of copper into sensitive device regions. Moreover, a second metal line 103B is formed within the second die region 120B, which may be comprised of the same metal as the metal line 103A. An etch stop layer 104 is formed on the dielectric layer 102 and the metal lines 103A and 103B, wherein the etch stop layer 104 may be comprised of a material that exhibits a high etch selectivity to the material of a dielectric layer 105 formed on the etch stop layer 104. Furthermore, the etch stop layer 104 may also act as a diffusion barrier between the metal lines 103A, 103B and neighboring materials to reduce the out-diffusion of metal, such as copper, and diffusion of dielectric material into the metal lines 103A, 103B.
The dielectric layer 105, which may be comprised of a low-k dielectric material, is formed on the etch stop layer 104, followed by an ARC layer or capping layer 106, which may be formed from two or more sub-layers so as to achieve the desired performance with respect to the optical behavior, mechanical strength and masking characteristics. For instance, the capping layer 106 may be provided as a stack including a silicon dioxide layer, acting to impart improved mechanical strength to the layer 105 when formed of a low-k material, and a silicon oxynitride layer for adapting the optical behavior and a thin silicon dioxide layer acting as a nitrogen barrier for a resist mask 107 formed on the capping layer 106. The resist mask 107 includes a first opening 107A above the first die region 120A that corresponds to a via opening 105A for electrically connecting the metal line 103A with a metal line still to be formed in the dielectric layer 105. The resist mask 107 further comprises a trench 105B for connecting to the metal line 103B so as to finally establish a die seal for enclosing the first region 120A, or any other metallic enclosure of a specified die portion, such as a measurement region.
A typical process flow for forming the semiconductor device 100 as shown in FIG. 1a may comprise the following processes. After the completion of any circuit elements within the substrate 101, the dielectric layer 102 may be deposited by well-established deposition recipes based on plasma enhanced chemical vapor deposition (PECVD). For example, the layer 102 may be comprised of silicon dioxide, fluorine-doped silicon dioxide or SiCOH and hence deposition recipes on the basis of appropriate precursors may be employed to form the layer 102. Then the metal lines 103A, 103B may be formed in accordance with processes as will be described in the following with reference to the layer 105. Thereafter, the etch stop layer 104 is deposited by, for instance, well-established PECVD with a thickness that is sufficient to reliably stop a via and trench etch process to be performed later on. Next, the dielectric layer 105 is formed by chemical vapor deposition (CVD) or spin coating, depending on the material used. Then, the capping layer 106 is formed by PECVD techniques on the basis of well-established recipes to provide the desired characteristics in the further processing of the device 100. Finally, the resist mask 107 may be formed by advanced photolithography to form the respective openings 107A, 107B. Thereafter, an anisotropic etch process is performed, wherein, in an initial phase, the exposed portion of the layer 106 is removed and, in a subsequent process, the dielectric material of the layer 105 is removed to form the openings 105A, 105B. During this anisotropic plasma etch process, etch-specific phenomena, called “wafer arcing,” may randomly occur, thereby generating burned metal and “worm-like” arcing marks, mainly along the edge of the substrate 101 and the metal line 103B, which may represent a metallic boundary for enclosing the first die region 120A. Thus, the frequency of the wafer arcing events significantly affects the yield per substrate, as such a wafer arcing event may result in a complete failure of one or more die regions. It is assumed that this frequency is substantially determined by plasma instabilities and by surface structure conditions, such as the topology, the pattern density, the presence of underlying metal lines, etc. For instance, research seems to indicate that the frequency of wafer arcing events during dielectric etch processes may be extremely low for front end processes and may significantly increase for back end processes when a plurality of metallization layers is already present, wherein in particular the via formation in the dual damascene approach tends to have a high probability for wafer arcing. Thus, after completion of the above-described etch process, one or more of the die regions 120B may have experienced a wafer arcing event, thereby typically rendering the corresponding die region 120A non-useable.
FIG. 1b schematically illustrates the device 100 in an advanced manufacturing stage. The device 100 now comprises a resist mask 109 having formed therein a trench 109A above the via opening 105A with dimensions corresponding to design dimensions of a trench to be formed above and around the via opening 105A. The resist mask 109 further comprises a trench 109B formed above the trench opening 105B in accordance with the dimensions thereof. Moreover, a fill material 108 is formed underneath the resist mask 109, wherein the fill material 108 is also provided within the openings 105A and 105B. The fill material may be comprised of a photoresist of different type compared to the resist mask 109, or the fill material 109 may represent any other polymer material that may be applied in a low viscous state so as to fill the openings 105A and 105B while providing a substantially planar surface. The fill material 108 may also serve as an ARC layer during the patterning of the resist mask 109.
The resist mask 109 may be formed by first applying the fill material 108 by, for example, spin-coating a resist or a polymer material, then applying a photoresist by spin coating, performing a well-established photolithography process and etching or dry-developing the fill material 108 on the basis of the resist mask 109. Thereafter, the device 100 is subjected to an etch ambient 110 on the basis of carbon and fluorine to etch through the layer 106 and remove a portion of the layer 105 to form a trench around the via opening 105A while the resist mask 109 and the fill material 108 at the trench opening 105B prevent substantial material removal. Moreover, the fill material 108 within the openings 105A and 105B, although also partially removed during the etch process 110, protects the remaining etch stop layer 104 so that the metal lines 103A and 103B are not exposed to the etch ambient 110. After a trench of specified depth is formed around the via opening 105A, the resist mask 109 and the fill material 108 are removed by, for instance, an oxygen-based plasma treatment.
FIG. 1c schematically shows the device after the above process sequence with a trench 111 formed in the layer 106 and the dielectric layer 105 around the via opening 105A. Moreover the device is subjected to a further etch process 112 to remove the remaining etch stop layer 104.
The via opening 105A, the trench 111 and the trench 105B may then be filled with metal, such as copper, copper alloys, by electrochemical deposition techniques, wherein, prior to the electrochemical deposition, corresponding barrier and seed layers may be formed. As pointed out above, during the formation of the metal-filled via 105A and the trench 111 in the first die region 120A and the trench 105B in the second die region 120B, an increased risk for wafer arcing may result, in particular during the etch process for forming the via 105A. Moreover, the risk for wafer arcing may still increase for each further metallization layer that is to be formed above the layer 105, thereby significantly reducing production yield.
In view of the situation described above, there exists a need for an improved technique which solves or at least reduces the effects of one or more of the problems identified above.